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Purpose: This paper aims to present assessment of models and simulation results used in the development process of flight stabilisation system that uses trim tabs for PZL-130 Orlik turboprop military trainer aircraft. Flight test of the system allowed to compare software and hardware simulation results with real flight recordings. Design/methodology/approach: Proposed flight stabilisation system was developed using modern techniques of model-based design, automatic code generation, software and hardware in the loop testing. The project reached flight testing stage which allowed to gather data to verify models and simulation results and asses their quality. Findings: Results of the comparison showed that the trim tab actuator model used in simulation can be improved by adding play. This reduced the difference between simulation and real flight system output – actuator angle. The influence of airloads on the flying actuator angle compared to hardware in the loop simulation in lab is less than ± 0.6°. Originality/value: Proposed flight stabilisation system that uses trim tabs has several benefits over classic automatic flight system in terms of weight, energy consumption and structure simplicity and does not need aircraft primary control modification. It was developed using modern techniques of model-based design, automatic code generation and hardware in the loop simulations. [ABSTRACT FROM AUTHOR]

Aircraft are composed of many electronic systems: sensors, displays, navigation equipment, and communication elements. These elements require a reliable interconnection, which is a major challenge for communication networks since high reliability and predictability requirements must be verified for safe operation. In addition, their verification via hardware deployments is limited because these are costly and it is difficult to try different architectures and configurations, thus delaying design and development in this area. Therefore, verification at early stages in the design process is of great importance and must be supported with simulation. In this context, this work presents an event-driven link-level framework and simulator for the validation of avionics networks. The tool presented supports communication protocols commonly used in avionics, such as Avionics Full-Duplex Switched Ethernet (AFDX), as well as Ethernet, which is used with static routing. Also, the simulator provides accurate results by employing realistic models for various devices. The proposed platform was evaluated in the Clean Sky's Disruptive Cockpit for Large Passenger Aircraft architecture scenario, showing the capabilities of the simulator. Verification speed is a key factor in its application, so the computational cost was analyzed, proving that the execution time is linearly dependent on the number of messages sent and that the increase in the number of nodes has few quadratic components. [ABSTRACT FROM AUTHOR]

Negative capacitance usually exists in ferroelectric materials, and its instinct nonlinearity and negative capacitance render its potential applications. To date, the single negative capacitance device is commonly unavailable. Hence, it is necessary to build a negative capacitor emulator in hardware for further investigating its electrical characteristics and applications. Based on a simple negative capacitor mathematical model, an emulator circuit that can mimic the S-shaped voltage–charge characteristics of the negative capacitor is proposed. The proposed emulator is composed of commercial off-the-shelf components, such as operational amplifiers, resistors, and capacitors. Based on the negative capacitor, we design a new chaotic circuit that can generate the single-period, double-period, single-scroll chaos, double-scroll chaos, and so on. The theoretical calculation, simulation analysis, and hardware experimental verification manifest that this proposed emulator circuit can be operated as a negative capacitor and applied in the chaotic circuit. [ABSTRACT FROM AUTHOR]

Transient execution attacks such as Spectre and Meltdown exploit speculative execution in modern microprocessors to leak information via cache side‐channels. Software solutions to defend against many transient execution attacks employ the lfence serialising instruction, which does not allow instructions that come after the lfence to execute out‐of‐order with respect to instructions that come before the lfence. However, errors and Trojans in the hardware implementation of lfence can be exploited to compromise the software mitigations that use lfence. The aforementioned security gap has not been identified and addressed previously. The authors provide a formal method solution that addresses the verification of lfence hardware implementation. The authors also show how hardware Trojans can be designed to circumvent lfence and demonstrate that their verification approach will flag such Trojans as well. The authors have demonstrated the efficacy of our approach using RSD, which is an open source RISC‐V based superscalar out‐of‐order processor. [ABSTRACT FROM AUTHOR]

Zero Trust Architecture requirements are of increasing importance in critical systems development. Zero trust tenets hold that no implicit trust be granted to assets based on their physical or network location. Zero Trust development focuses on authentication, authorization, and shrinking implicit trust zones to the most granular level possible, while maintaining availability and minimizing authentication latency. Performant, highassurance cryptographic primitives are thus central to successfully realizing a Zero Trust Architecture. The Rust programming language has garnered significant interest and use as a modern, type-safe, memory-safe, and potentially formally analyzable programming language. Our interest in Rust particularly stems from its potential as a hardware/software co-assurance language for developing Zero Trust Architectures. We describe a novel environment enabling Rust to be used as a High-Level Synthesis (HLS) language, suitable for secure and performant Zero Trust application development. Many incumbent HLS languages are a subset of C, and inherit many of the well-known security shortcomings of that language. A Rust-based HLS brings a single modern, type-safe, memory-safe, high-assurance development language for both hardware and software. To study the benefits of this approach, we crafted a Rust HLS subset, and developed a frontend to the hardware/software coassurance toolchain due to Russinoff and colleagues at Arm, used primarily for floating-point hardware formal verification. This allows us to leverage a number of existing hardware/software co-assurance tools with a minimum investment of time and effort. In this paper, we describe our Rust subset, detail our prototype toolchain, and describe the implementation, performance analysis, formal verification and validation of representative Zero Trust algorithms and data structures written in Rust, emphasizing cryptographic primitives and common data structures. [ABSTRACT FROM AUTHOR]

The satisfiability problem (SAT) in propositional logic determines if there is an assignment of values that makes a given propositional formula true. Recently, fast SAT solvers have been developed, and SAT encoding research has gained attention. This enables various real-world problems to be transformed into SAT and solved, realizing a solution to the original problems. We propose a new encoding method, Fractional Encoding, which focuses on the At-Most-K constraints—a bottleneck of computational complexity—and reduces the scale of logical expressions by dividing target variables. Furthermore, we confirm that Fractional Encoding outperforms existing methods in terms of the number of generated clauses and required auxiliary variables. Hence, it enables the efficient solving of real-world problems like planning and hardware verification. [ABSTRACT FROM AUTHOR]

We introduce Go2Pins, a tool that takes a program written in Go and links it with two model checkers: LTSMin (Kant et al. Ltsmin: high-performance language-independent model checking. In: TACAS'15, pp. 692–707, 2015) and Spot (Duret-Lutz et al. Spot 2.0-a framework for LTL and ω automata manipulation. In: ATVA'16, vol. 9938 of LNCS, pp. 1294, 122–129, 2016). Go2Pins is an effort to promote the integration of both formal verification and testing inside industrial-size projects. With this goal in mind, we introduce black-box transitions, an efficient and scalable technique for handling the Go runtime. This approach, inspired by hardware verification techniques, allows easy, automatic and efficient abstractions. Go2Pins also handles basic concurrent programs through the use of a dedicated scheduler. Moreover, in order to efficiently handle recursive programs, we introduce PSL R E C , a formalism that augments PSL without changing the complexity of the underlying verification process. In this paper we demonstrate the usage of Go2Pins over benchmarks inspired by industrial problems and a set of LTL formulae. Even if Go2Pins is still at the early stages of development, our results are promising and show the benefits of using black-box transitions. This paper also shows how Go2Pins is able to work efficiently on two bugs coming from industrial problems Kubernetes and Trillian. [ABSTRACT FROM AUTHOR]

Under partial shading conditions (PSCs), the output characteristic curve of PV system fluctuates, hence contains multiple peaks. The higher efficiency of the Global Maximum Power Point(GMPP) tracking technique becomes a must to the Photovoltaic(PV) system, therefore, an algorithm based on Tuna Swarm Optimization (TSO) is proposed in this study. Then, it is applied to track the global MPPT of PV system under partial shading conditions, six shading scenarios have been considered. This method is on a PV system consisting of five panels that are formed in a MATLAB/Simulink platform. And then Particle Swarm Optimization(PSO) algorithm, Black Widow Spider(BWO), Squirrel Search Algorithm(SSA) and TSO are compared, the outcomes are analyzed in detail. The proposed algorithm reached maximum power of over 97% under the six PSCs. And the response time in all six scenarios were between 0.2s and 0.4s. This value is good compared to the other three algorithms. Finally, hardware verification demonstrate the performance and feasibility of the proposed MPPT. The proposed method reached maximum power over 91% in the Hardware-in-loop(HIL) and Rapid Control Prototype(RCP) platform. [Display omitted] • A novel MPPT method based on TSO technique is proposed, which can operate stably and efficiently in PV system. • TSO has not been reported in the application of MPPT for PV systems under shading conditions. • Improve various performance indicators in the MPPT process, such as convergence speed and tracking accuracy are significantly improved, tracking efficiency is effectively improved, and the process is stable. • Six shading scenarios and three other control methods are constructed to compare and analyze the performance parameters of all methods in MATLAB/Simulink platform. • The PV system model is divided into three parts. The three parts are uploaded into Starsim-HIL, FPGA and Starsim-RCP. [ABSTRACT FROM AUTHOR]

Coverage is a key indicator for verification progress, verification closure, and verification sign-off in an integrated circuit design. The notion of coverage management, namely, the use of coverage information across the design hierarchy to identify verification loopholes, is well understood in the digital context, but requires considerable disambiguation in the analog/mixed-signal (AMS) context. This article develops the core artifacts of AMS coverage and presents a comprehensive coverage management approach based on our tool, CoveRT. Our results, gleaned from live industrial designs, demonstrate the benefits of AMS coverage management across the design hierarchy, both in terms of identifying verification gaps, as well as in finding design bugs. [ABSTRACT FROM AUTHOR]

As software becomes more complex, it becomes more difficult to verify its correctness. This poses a particular problem for autonomous systems, since they are software-intensive and will also require strong evidence of correctness in order to be allowed to operate in the real world. One way to help address this problem is through the use of formal methods, i.e. mathematicallybased tools for software and hardware verification. In this paper, we perform formal program verification on a service in OpenUxAS, a free and open source software framework for mission-level, multi-vehicle autonomy. More specifically, we apply the SPARK language and verification toolset to a service that sanity-checks and segments long sequences of vehicle waypoints to prove that it is free of runtime errors. [ABSTRACT FROM AUTHOR]

This paper presents a hardware implementation upon a Field Programmable Gate Array (FPGA) of improved Vector Control Strategies (VCSs) based on a Fuzzy Logic System (FLS) of a grid-connected wind energy conversion system. Usually, the classical VCS is based on fixed-gain Proportional Integral Derivative (PID) controllers, which are known to exhibit limited performance against the nonlinear behavior of wind systems, such as rapid fluctuations of the wind speed and uncertainties of the system parameters. In order to overcome this limitation, an improved VCS based on Fuzzy Gain Scheduling PID controllers (VCS-FGS-PID) is suggested in this work to guarantee good tracking, high accuracy and good robustness under system parameter variations. Indeed, the PID controller gains are tuned, in real-time, by the FLS. In addition, the proposed VCS-FGS-PID methods are implemented on the FPGA in order to reduce the delays and the period of the system of the control loop, thanks to its parallel processing. In fact, the performance of the suggested VCS-FGS-PID approaches are proved by digital simulation with the Xilinx system generator tool under Matlab/Simulink, in addition to an experimental hardware-in-the-loop implementation using the FPGA. The obtained results demonstrate that the proposed VCS-FGS-PID techniques offer better performance as regards good tracking and high accuracy and good robustness against stator resistance variability compared to VCS-PI. [ABSTRACT FROM AUTHOR]

Compared with the conventional pulse-shaping transmission system, the full Nyquist rate transmission system with large bandwidth is sensitive to the sampling phase. It has only one sample available in one symbol period and is easily interfered by the channel, which does not allow the traditional symbol synchronization methods to be used directly. Another challenge is that the resource utilization for sampling data processing needs to be minimized due to the excessive consumption of the high data throughput in hardware resources. To solve these issues, we propose a symbol synchronization method based on the combination of software and hardware, which mainly includes two processes: Obtaining the initial phase by using Chirp signal and MOE criterion before communication; tracking the real-time phase using an on-line gradient table and frequency domain analysis of known data during communication. Both processes are proceeded with a phase adjustable clock. Through hardware verification, the sampling phase can be kept close to the optimal phase, thus ensuring the accuracy of the sampling data, and improving the system BER performance. [ABSTRACT FROM AUTHOR]

The Extreme Universe Space Observatory on a Super Pressure Balloon 2 (EUSO-SPB2), in preparation, aims to make the first observations of Ultra-High Energy Cosmic Rays (UHECRs) from near space using optical techniques. EUSO-SPB2 will prototype instrumentation for future satellite-based missions, including the Probe of Extreme Multi-Messenger Astrophysics (POEMMA) and K-EUSO. The payload will consist of two telescopes. The first is a Cherenkov telescope (CT) being developed to quantify the background for future below-the-limb very high energy (E > 10 PeV) astrophysical neutrino observations, and the second is a fluorescence telescope (FT) being developed for detection of UHECRs. The FT will consist of a Schmidt telescope, and a 6192 pixel ultraviolet camera with an integration time of 1.05 μ s. The first step in the data acquisition process for the FT is a hardware level trigger in order to decide which data to record. In order to maximize the number of UHECR induced extensive air showers (EASs) which can be detected, a novel trigger algorithm has been developed based on the intricacies and limitations of the detector. The expected performance of the trigger has been characterized by simulations and, pending hardware verification, shows that EUSO-SPB2 is well positioned to attempt the first near-space observation of UHECRs via optical techniques. [ABSTRACT FROM AUTHOR]

The behaviour and effective performance of solar cell is represented by Triple Diode Solar Cell Module (TDSCM) circuit with five parameters for different environmental conditions. The equations described the solar modules behaviour are usually implicit in nature and the parameter extraction was very complexity. From the Photovoltaic (PV) module data sheet, one can identify the four equations applying to single, double, and triple diode parameters. For getting fifth equation researchers have gone with several approximations, which concludes the computation complexity, convergence problem, and low accuracy issues. In the proposed work the fifth equation are framed under the area characteristics curve (V-I & P-V) concept using Simpson's approximation. To find which PV module is less accuracy and non-linearity consideration for the performance level. Therefore, to overcome these issues the multi-objective Genetic Algorithm (GA) optimization method are prescribed to frame the fifth equation of the Simpson's rules. This works improved non-linearity performance and gives the high accuracy modelling compare to other single, double diode methods. [ABSTRACT FROM AUTHOR]

Using field-programmable gate arrays (FPGAs) for software and hardware verification and development is a standard step in the digital application-specific integrated circuits (ASICs) design flow. However, asynchronous FPGAs are not available on the market and commercially available FPGAs provide support only for synchronous circuits. Although a lot of research effort has been undertaken in order to use synchronous FPGA to map asynchronous circuits, proposed solutions are typically lacking automation and target-specific circuit style and sometimes specific FPGA vendor. In this work, we present an automated solution for asynchronous circuits mapping onto the synchronous FPGAs. We build a synchronous model of the original asynchronous circuit based on the event-driven simulation concepts. The proposed approach supports a wide range of circuit styles, including those with various timing assumptions and complex circuitry structures incompatible with the standard synchronous flow. We avoid using vendor-specific features so that the model we generate can be implemented on any commercially available FPGA. We provide an extensive evaluation of our solution and demonstrate that our approach results in a speedup factor of $1.3\times 10^{5}$ against an asynchronous circuit simulator, $2.8\times 10^{4}$ against commercial digital simulators, and is 16.5 times slower than the expected performance of the original asynchronous circuit implemented as an ASIC. [ABSTRACT FROM AUTHOR]

This study focuses on development, task planning, and dynamic analysis of a previously proposed spherical parallel robot manipulator that is conceptually enhanced to adapt various brain surgery scenarios. Conceptual design of the proposed manipulator was briefly introduced and explained. In order to simulate one of the possible surgery scenarios, a case study of craniotomy was designed along with its trajectory planning. Dynamic analysis of proposed manipulator was performed by Lagrange method, and required actuator torque values were calculated for the desired trajectory. At the end of the study, hardware verification was carried out on the manufactured prototype of the system by comparing both calculated/acquired torque values and desired/actual trajectories. Promising verification results in terms of system dynamics and trajectory execution were introduced. [ABSTRACT FROM AUTHOR]

• Minimize the latency caused by communication with off-chip memory. • Implement a design with optimized components following a divide and conquer process. • Reduce the resources use by CAD tool and force some area optimizations using p-blocks. • The pre-implementated flow improves the productivity. In recent years, Convolution Neural Networks (CNN) have been extensively adopted in broad Artificial Intelligence (AI) applications and have demonstrated ability and effectiveness in solving learning problems. However, developing high-performance hardware accelerators on Field Programmable Gate Array (FPGA) for CNNs often demands skills in hardware design and verification, accurate distribution localization, and long development cycles. Besides, the depth of CNN architectures increases by reusing and replicating several layers. In this work, we take advantage of the replication of CNN layers to achieve improvement in design performance and productivity. We propose a programming flow for CNNs on FPGA to generate high-performance accelerators by assembling CNN pre-implemented components as a puzzle based on the graph topology. Using pre-implemented components allows us to use minimum of resources, predict the performance, and gain in productivity since there is no need to synthesize any Hardware Description Language (HDL) source code. Furthermore, the pre-implemented components are reused for different range of applications, reducing the engineering time. Through prototyping, we demonstrate the viability and relevance of our approach. Experiments show a productivity improvement of up to 69% compared to a traditional FPGA implementation while achieving over 1.75× higher Fmax with lower resources and higher energy efficiency. [ABSTRACT FROM AUTHOR]

This special issue contains six revised and extended versions of tool papers that appeared in the proceedings of TACAS 2021, the 27th International Conference on Tools and Algorithms for the Construction and Analysis of Systems. The issue is dedicated to the realization of algorithms in tools and the studies of the application of these tools for analysing hard- and software systems. [ABSTRACT FROM AUTHOR]

Frequency stability is a critical factor in maintaining the quality of the power grid system. A battery energy storage system (BESS) with quick response and flexibility has recently been used as a primary frequency control (PFC) resource, and many studies on its control algorithms have been conducted. The cyber physic system (CPS) simulator, which can perform virtual physical modelling and verification of many hardware systems connected to the network, is an optimal solution for the performance verification of control algorithms and hardware systems. This study introduces a large-scale real-time dynamic simulator that includes the national power system. This simulator comprises a power grid model, an energy management system (EMS) model, a BESS system model, and a communication model. It performs the control algorithm performance evaluation and the hardware controller's response performance evaluation. The performance of the control algorithm was evaluated by tracking the power system's characteristic trajectory in the transient state based on the physical response delay time between the output instruction of the frequency regulation controller (FRC), a hardware controller, and the output response of the BESS. Based on this, we examined the response performance evaluation results by linking them to the optimally designed actual FRC. As a result, we present an analysis of the BESS's characteristic trajectories in the transient state, such as frequency, power system inertia, and power grid constant, and provide FRC response performance evaluation results at a level of 163 ms, by connecting the BESS installed at the actual site with the CPS simulator. [ABSTRACT FROM AUTHOR]

Aiming at the problems of long acquisition time, high algorithm complexity and high resource overhead in short-term burst communication, a high-precision synchronization scheme is designed in this paper. The scheme customizes the frame structure of both sender and receiver, adopts a unique code differential matching algorithm to achieve signal detection and frame synchronization, and adopts a forward estimation algorithm based on pilot cumulants to achieve frequency offset estimation and correction. In order to take into account the accuracy of frequency offset estimation and the complexity of the algorithm, the sliding correlation algorithm is used for the unique code to realize the initial phase acquisition, which makes the system compact and more suitable for FPGA hardware implementation. Theoretical analysis and software simulation show that the scheme has good reception performance under the condition of low signal-to-noise ratio and high dynamic range, and the frequency estimation accuracy can reach one ten thousandth of the symbol rate. Hardware co-simulation and verification are carried out in this paper, and the corresponding simulation waveforms are given. [ABSTRACT FROM AUTHOR]

As one of the core technologies of electric vehicles (EVs), the state of charge (SOC) estimation algorithm of lithium-ion batteries is directly related to the performance of the battery management system (BMS). Before EVs are put into the market, the SOC estimation algorithm must be tested and verified to ensure the reliability of the BMS and the safe operation of EVs. Therefore, this paper establishes a lithium-ion batteries' SOC estimation algorithm verification platform for the comprehensive performance evaluation and verification of the new SOC estimation algorithm. In addition, there are two schemes, including real-time SOC estimation verification and offline SOC estimation verification can be selected, which improve the reliability and efficiency of verification. Firstly, the design idea of the verification platform (the research and development purpose, functional requirements, and the overall design scheme) is introduced in detail. Secondly, the modular design idea is used to design the hardware structure of the verification platform, which mainly includes the BMS host module, BMS slave module, battery charger module, and electronic load module. Finally, the software system, including the communication architecture, the SOC reference standard and evaluation indexes of the algorithm, and the upper computer function and implementation is designed to realize the functions of the verification platform. [ABSTRACT FROM AUTHOR]

Limited by satellite load and carrying capacity, it is difficult for inter-satellite link systems to improve information transmission capabilities by increasing power and antenna size like traditional terrestrial communication systems. Satellite communication payload power has always been an important limitation of long-distance communication performance. In order to improve the satellite's long-distance communication capability and comprehensively consider the characteristics of Doppler frequency changes in the satellite environment, we propose a cooperative communication algorithm based on weak bit feedback. This algorithm can realize the time and space focusing of the beams emitted by multiple distributed satellite nodes at the destination node, and improve the performance of satellite long-distance communication. This paper simulates the above algorithm based on STK/Matlab software. The simulation results show that the weak bit feedback algorithm has stronger adaptability, faster convergence speed and higher synthesis efficiency under different channel changes. The algorithm is simple and easy to implement, and is suitable for the inter-satellite link environment with many satellite nodes and high scalability. Finally, we conducted hardware experimental verification, analyzed the signal flow of each module in the hardware, and tested it on the USRP software radio platform. The test results show that it is a feasible solution to realize distributed satellite node cooperative communication based on the weak bit feedback algorithm. [ABSTRACT FROM AUTHOR]

In a multi-node spacecraft or unmanned aerial vehicle (UAV) group, a multifunctional signal containing measurement, navigation, and communication functions is required to simplify the receiver structure, and to increase spectrum utilization. The paper proposes a multifunctional signal based on a binary offset carrier (BOC) and binary phase shift keying (BPSK) modulation. The signals which carry different functions are orthogonal in the frequency domain, which causes the data transmission signal to not be affected by BOC signal. In addition, in the high carrier to noise ratio (C/N0), the spreading gain of the BOC signal ensures that the communication signal has a slight influence on navigation signals. Moreover, the multifunctional signal can achieve communication and measurement functions at the same frequency point and fast switching in multinodes. These advantages can simplify the receiver design and improve the frequency band utilization. Finally, in this study we completed the design and verification of the hardware system. [ABSTRACT FROM AUTHOR]

Constrained random stimulus generation is no longer sufficient to fully simulate the functionality of a digital design. The increasing complexity of today's hardware devices must be supported by powerful development and simulation environments, powerful computational mechanisms, and appropriate software to exploit them. Reinforcement learning, a powerful technique belonging to the field of artificial intelligence, provides the means to efficiently exploit computational resources to find even the least obvious correlations between configuration parameters, stimuli applied to digital design inputs, and their functional states. This paper, in which a novel software system is used to simplify the analysis of simulation outputs and the generation of input stimuli through reinforcement learning methods, provides important details about the setup of the proposed method to automate the verification process. By understanding how to properly configure a reinforcement algorithm to fit the specifics of a digital design, verification engineers can more quickly adopt this automated and efficient stimulus generation method (compared with classical verification) to bring the digital design to a desired functional state. The results obtained are most promising, with even 52 times fewer steps needed to reach a target state using reinforcement learning than when constrained random stimulus generation was used. [ABSTRACT FROM AUTHOR]

Hardware verification of modern electronic systems has been identified as a major bottleneck due to the increasing complexity and time-to-market constraints. One of the major objectives in hardware verification is to drastically reduce the validation and debug time without sacrificing the design quality. Assertion-based verification is a promising avenue for efficient hardware validation and debug. In this article, we provide a comprehensive survey of recent progress in assertion-based hardware verification. Specifically, we outline how to define assertions using temporal logic to specify expected behaviors in different abstraction levels. Next, we describe state-of-the art approaches for automated generation of assertions. We also discuss test generation techniques for activating assertions to ensure that the generated assertions are valid. Finally, we present both pre-silicon and post-silicon assertion-based validation approaches that utilize simulation, formal methods aswell as hybrid techniques.We concludewith a discussion on utilizing assertions for verifying both functional and non-functional requirements. [ABSTRACT FROM AUTHOR]

The maximum power point tracking (MPPT) is an essential function of the PV power system to achieve the maximum PV power utilization. Traditionally, the MPPT can be realized by a duty cycle modulated dc–dc converter. However, if the LLC resonant converter is considered for the PV power system, the frequency-modulated MPPT algorithm should be adopted. Several strategies such as the frequency-based perturbation and observation (P&O) method and the center point iteration (CPI) method were proposed for the LLC resonant converter. However, with the conventional P&O method, there will be a tradeoff between the tracking speed and the oscillation phenomenon. Besides, the CPI method is unable to maintain the maximum power output under varying environmental conditions. In view of this, an optimal frequency-modulated hybrid MPPT algorithm is proposed in this article. First, the proposed frequency-modulated impedance-matching (FMIM) method is developed to track an optimal operation point under present environmental conditions. Then, the P&O concept will be utilized to ensure maximum power harvesting from the PV array. On the other hand, the operation point calculated via the FMIM is very close to the real MPP. Therefore, the perturbation amount of the P&O method can be minimized to avoid the oscillation around the maximum power point. Operational principles and thorough mathematical derivations are also developed. Finally, both simulation results and hardware verifications obtained from a 500-W prototype circuit demonstrate the performance and feasibility of the proposed MPPT. [ABSTRACT FROM AUTHOR]

Model checking with a time aspect is often used in verification on hardware and embedded systems. Timed automata are often used for such models. UPPAAL is a world-wide famous model checking tool for timed automata; however, UPPAAL is a Computational Tree Logic (CTL)-based model checking tool and cannot use Linear Temporal Logic (LTL) properties. Bounded model checking uses LTL (Linear Time Logic) for a checking formula. Bounded model checking specifies a boundary k and obtains counterexamples by searching from the initial state of a system to states reachable by k-steps. There are several studies on bounded model checking. Sorea has proposed a concrete algorithm for a timed automaton. There are, however, no clear details on how to implement bounded model checking tools for timed automata, and study the performance. Another problem is that the timed automaton covered by the method does not support general variables except for clock variables. The objective of this study is to implement a bounded model checking tool using LTL for timed automata. We also improve Sorea's method so that it can handle extended timed automata that handle general variables. This paper also presents some LTL examples from texts on requirement specifications for embedded systems and the results of applying the tool to them. [ABSTRACT FROM AUTHOR]

Security vulnerabilities provide attackers unauthorized access to critical resources and effective attack surfaces to compromise a system. Security verification is an emerging technique for detecting and locating such threats. However, existing security verification methods are typically restricted within the hardware or software boundary and incapable of meeting cross-layer verification requirements due to the differences in design semantics and the lack of a security model that fits both hardware and software. We attempt to address such a limitation from the perspective of information flow analysis and propose a hardware/software security co-verification method, which can check information flow security properties on fine-grained hardware information flow models. The proposed method can pinpoint security vulnerabilities by capturing information flow security property violations under clues of malicious information flows. Our information flow security model and properties are described using standard hardware design and verification languages, which allows our method to be seamlessly integrated with electronics design automation flows. Experimental results using RISC-V hardware/software designs show that the proposed method detects software, hardware and system-level security vulnerabilities, effectively. • Developing a formal model for precisely modeling information flows in both HW and SW. • Proposing a HW/SW security co-verification method using standing EDA tools. • Providing a vulnerability detection method through formal security co-verification. [ABSTRACT FROM AUTHOR]

Finite Rate of Innovation (FRI) sampling theory offers an efficient approach for the sub-Nyquist measurement of the short pulse stream signal, but it can only address parameter measurement problems under waveform consistency. To overcome the measurement challenge of the hybrid pulse streams, this paper proposes a subspace projection-based FRI parameter estimation method under sub-Nyquist sampling conditions. Our method is based on the concept of subspace decomposition, which involves finely dividing different pulse signals within their respective Shift-invariant (SI) subspaces. We use the generating function of the corresponding space as a decoupling object to achieve parameter estimation through FRI measurement methods. The sampling process is efficient and simple, requiring only single-channel sampling to measure the characteristic parameters of all hybrid pulses. We not only provide theoretical guarantees for the implementation of this approach but also conduct numerous numerical simulations and hardware verification experiments. Our experimental results demonstrate that our method achieves higher parameter measurement accuracy compared to classical methods in a simpler manner. • The extensibility of FRI sampling theory. • High-precision distortion reconstruction of hybrid pulse streams. • Realizing signal pattern transformation through subspace projection. [ABSTRACT FROM AUTHOR]

The article explores the growth of the semiconductor industry over the last couple of decades has caused the design and manufacturing process for microelectronics to become global in nature, creating very complex and opaque supply chains. A typical semiconductor production process spans several countries, multiple states, and makes numerous trips around the world.

A new comparison-to-reference performance verification technique compares an ${E}$ -band channel-sounder (CS) and reference vector network analyzer (VNA) measurements of the same controlled, static channel. This new technique reduces the number of inaccurate assumptions that exist in other methods providing a stronger verification of the CS hardware and processing performance. This technique compares the CS and VNA-derived channel metrics from these measurements. Using mechanical switches, we established a controlled, static RF channel. The VNA has a comprehensive uncertainty analysis that propagates systematic and random uncertainties through to the power delay profiles. The method is suitable for millimeter-wave CS hardware with removable antennas. [ABSTRACT FROM AUTHOR]

Summary: In this paper, a three‐phase single‐stage grid‐connected photovoltaic (PV) system with active power filtering capability by means of a three‐level T‐type inverter is presented. The system is intended to fulfill many functions: harmonic mitigation, unity power factor operation, maximum power extraction from PV source, and so on. For the proposed system to achieve these tasks with a good dynamic performance, a new control strategy based on the fuzzy logic controller is developed. Fuzzy control has three main stages and each one requires many settings or selection of parameters. A new approach of setting the scaling factors which considerably affect the system's response is proposed. Furthermore, a methodology to properly set the fuzzy rules is suggested. The electrical power chain of the system comprises a farm of a PV source, three‐level T‐type inverter space vector pulse width modulation controlled, inductor filter, non‐linear load, and the utility grid. To evaluate the performance of the proposed control, a processor‐in‐the‐loop is performed as a hardware verification of the inverter control algorithm using a low‐cost STM32F4 discovery board, while the power circuit plant is modeled in the host computer using Matlab/Simulink. The obtained results are very satisfactory and confirm the role of each component, especially in terms of maximum power tracking, power quality, unity power factor operation, and control robustness. [ABSTRACT FROM AUTHOR]

In this article, an analytical concept and hardware verification of the time-varying infinite impulse response narrow multiband-stop filter with nonzero initial conditions are presented. The time variability of the filter parameters and nonzero initial conditions are introduced to the filter structure in order to reduce its transient response. Such a filter can be very useful in various measurement systems. In particular, short transient filters are very desirable for processing signals whose initial part is of great importance. In this article, the algorithm for finding the length of the initial conditions vector is presented. As an example, the proposed IIR multinotch filter is used for removing power-line interferences from the ECG signal. Computer simulations, hardware verification, and performance indices demonstrate that the proposed time-varying IIR multinotch filter with nonzero initial conditions possesses much better properties than the traditional time-invariant filter with zero initial conditions. [ABSTRACT FROM AUTHOR]

An autonomous monitoring and control system of unmanned surface vehicle (USV) with mobile water quality monitoring, sampling, and oxygenation functions is constructed. The control hardware and monitoring configuration software of the system is designed, respectively, which can be installed on USV and its remote control and monitoring terminal. The kinematic modeling of USV, waypoint trajectory-tracking control, distributed controller, simulation of tracking control, and verification of software and hardware design are carried out. In order to reject the system noise and external noise, a states estimation method with fully observable states is considered in the control law design. The software and hardware are also implemented to verify the effectiveness of the monitoring platform. Through setting a series of monitoring target points and monitoring parameters in the configuration software of the remote user terminal or in the APP of the mobile user terminal, the USV can realize the automatic cruise monitoring using an autonomous navigation and tracking control algorithm, and quantitative water sampling collection. The reliability of the system is verified by the experiment of the shore test station, and the waypoint trajectory tracking and sensors data are replaying in a logview GUI of MOOS-Ivp and APP. [ABSTRACT FROM AUTHOR]

Adaptive oscillators (AOs) are nonlinear oscillators with plastic states that encode information. Here, an analog implementation of a four-state adaptive oscillator, including design, fabrication, and verification through hardware measurement, is presented. The result is an oscillator that can learn the frequency and amplitude of an external stimulus over a large range. Notably, the adaptive oscillator learns parameters of external stimuli through its ability to completely synchronize without using any pre- or post-processing methods. Previously, Hopf oscillators have been built as two-state (a regular Hopf oscillator) and three-state (a Hopf oscillator with adaptive frequency) systems via VLSI and FPGA designs. Building on these important implementations, a continuous-time, analog circuit implementation of a Hopf oscillator with adaptive frequency and amplitude is achieved. The hardware measurements and SPICE simulation show good agreement. To demonstrate some of its functionality, the circuit's response to several complex waveforms, including the response of a square wave, a sawtooth wave, strain gauge data of an impact of a nonlinear beam, and audio data of a noisy microphone recording, are reported. By learning both the frequency and amplitude, this circuit could be used to enhance applications of AOs for robotic gait, clock oscillators, analog frequency analyzers, and energy harvesting. [ABSTRACT FROM AUTHOR]

The functional verification process is one of the most expensive steps in integrated circuit manufacturing. Functional coverage is the most important metric in the entire verification process. By running multiple simulations, different situations of DUT functionality can be encountered, and in this way, functional coverage fulfillment can be improved. However, in many cases it is difficult to reach specific functional situations because it is not easy to correlate the required input stimuli with the expected behavior of the digital design. Therefore, both industry and academia seek solutions to automate the generation of stimuli to reach all the functionalities of interest with less human effort and in less time. In this paper, several approaches inspired by genetic algorithms were developed and tested using three different designs. In all situations, the percentage of stimulus sets generated using well-performing genetic algorithms approaches was higher than the values that resulted when random simulations were employed. In addition, in most cases the genetic algorithm approach reached a higher coverage value per test compared to the random simulation outcome. The results confirmed that in many cases genetic algorithms can outperform constrained random generation of stimuli, that is employed in the classical way of doing verification, considering coverage fulfillment level per verification test. [ABSTRACT FROM AUTHOR]

The article discusses the applied failure analysis tools and techniques toward integrated circuit trust and assurance. Topics discussed include these trends have introduced new vulnerabilities into the design and fabrication lifecycle that present significant trust issues as it relates to the assurance of manufactured chips; and this gap in current verification and validation practices has coalesced researchers toward developing new techniques for determining assurance of integrated circuits.

This article presents techniques into prediction and control of the radiated harmonic levels in time-modulated antenna arrays (TMAs). The effect of ramping on the controlling switching waveform, due to slew in the RF switches, is analyzed first. This is followed by a novel technique for controlling and reducing the fundamental carrier component (due to the Fourier series 0 Hz term) that is always produced by TMAs. A new bespoke, steerable, TMA RF hardware test platform is presented, using three gain states to pragmatically implement the proposed carrier reduction technique. The platform implementation utilizes binary logic control interfaces to the TMA, rather than analog control interfaces. Laboratory measurements using the test platform demonstrate a 16.5 dB reduction (limited by PCB emissions) in the level of the fundamental carrier component relative to the steered first harmonic, from a possible reduction of 21.3 dB. The array gain for the first harmonic beam is 2 dBi. [ABSTRACT FROM AUTHOR]

Temporal logic has become essential for various areas in computer science, most notably for the specification and verification of hardware and software systems. For the specification purposes rich temporal languages are required that, in particular, can express fairness constraints. For linear-time logics which deal with fairness in the linear-time setting, one-pass and two-pass tableau methods have been developed. In the repository of the CTL-type branching-time setting, the well-known logics ECTL and ECT L + were developed to explicitly deal with fairness. However, due to the syntactical restrictions, these logics can only express restricted versions of fairness. The logic CT L ⋆ , often considered as 'the full branching-time logic' overcomes these restrictions on expressing fairness. However, CT L ⋆ is extremely challenging for the application of verification techniques, and the tableau technique, in particular. For example, there is no one-pass tableau construction for CT L ⋆ , while one-pass tableau has an additional benefit enabling the formulation of dual sequent calculi that are often treated as more 'natural' being more friendly for human understanding. These two considerations lead to the following problem - are there logics that have richer expressiveness than ECT L + , allowing the formulation of a new range of fairness constraints with 'until' operator, yet 'simpler' than CT L ⋆ , and for which a one-pass tableau can be developed? Here we give a positive answer to this question, introducing a sub-logic of CT L ⋆ called ECT L # , its tree-style one-pass tableau, and an algorithm for obtaining a systematic tableau, for any given admissible branching-time formulae. We prove the termination, soundness and completeness of the method. As tree-shaped one-pass tableaux are well suited for the automation and are amenable for the implementation and for the formulation of sequent calculi. Our results also open a prospect of relevant developments of the automation and implementation of the tableau method for ECT L # , and of a dual sequent calculi. [ABSTRACT FROM AUTHOR]

In the last few years, satellite on-board data handling bandwidth requirements grew significantly, as well as production volume of these systems. A series of different protocols currently try to answer this need. In particular, the European Space Agency developed an open protocol solution: SpaceFibre. The SpaceFibre protocol can sustain a line rate of 6.25 Gb/s per lane (up to 16 lanes). It offers advanced and flexible Quality-of-Service features, as well as Fault Detection Isolation and Recovery services. The protocol structure has been developed so that full hardware implementation of its core layers is straightforward, granting high performances at low price in terms of complexity and power consumption, one of the most stringent requirements in space applications. In this paper, a FPGA implementation on both rad-hardened (RTAX2000, RTG4, Virtex-5) and commercial (ZYNQ 7000) devices of the SpaceFibre CODEC is presented together with its verification environment and a hardware validation set-up. Particular attention is given to the trade-off between resources utilisation, power consumption and CODEC configurations, in order to enable future system adopters to efficiently explore the design space. • Satellite on-board data-handling bandwidth is increasing up to tens of Gbps. • SpaceFibre is the upcoming protocol promoted by ESA to handle such requirement. • SpaceFibre can sustain 6.25gbps per lane (up to 16 lanes in parallel). • It offers advanced quality of service, fault detection isolation and recovery. • SpaceFibre codec development with performance analysis is carried out. [ABSTRACT FROM AUTHOR]

In this paper, we will study a particular subvariety of Hilbert algebras with a modal operator □ , called Lax Hilbert algebras. These algebras are the algebraic semantic of the □ , → -fragment of a particular intuitionistic modal logic, called Propositional Lax Logic (PLL ), which has applications to the formal verification of computer hardware. These algebras turn to be a generalization of the variety of Heyting algebras with a modal operator studied, under different names, by Macnab (Algebra Univ 12:5–29, 1981), Goldblatt (Math Logic Q 27(31–35):495–529, 1981; J Logic Comput 21(6):1035–1063, 2010) and by Bezhanishvili and Ghilardi (Ann Pure Appl Logic 147:84–100, 2007). We shall prove that the set of fixpoints of a Lax Hilbert algebra A , □ is a Hilbert algebra such that its dual space is homeomorphic to the subspace of reflexive elements of the dual space of A. We will define the notion of subframe of a Hilbert space X , K , and we will prove that there is a 1–1 correspondence between subframes of X , K and binary relations Q ⊆ X × X such that X , K , Q is a Lax Hilbert space. In addition, we will define the notion of subframe variety and we will prove that any variety of Hilbert algebras is a subframe variety. [ABSTRACT FROM AUTHOR]

Aiming at the problems of high cost, increased volume, low reliability, and environmental interference caused by sensor installation on permanent magnet synchronous motor, estimation method for motor speed and rotor position is proposed based on iterated cubature Kalman filter algorithm and applied to permanent magnet synchronous motor sensorless control. First, discrete mathematical model of permanent magnet synchronous motor in α-β coordinate system is established. Then, based on cubature Kalman filter and iterated cubature Kalman filter, simulation model of sensorless vector control system with dual closed-loop of permanent magnet synchronous motor speed and current is established. Also, simulation verification of two working conditions with given rotation speed and load is carried out. Finally, hardware experimental verification platform is built based on TMS320F28335 chip. Both simulation analysis and experimental results show that iterated cubature Kalman filter application to sensorless control of permanent magnet synchronous motor demonstrates good anti-load variation interference, stable motor operation, high motor speed and rotor position estimation accuracy, which suits the application with high requirement for precise motor control and mean important reference value and promotion significance. [ABSTRACT FROM AUTHOR]

Aiming at the problem of low intellectualization of program controlled unmanned aerial vehicle （UAV），intelligent correction method for flight control system based on online simulation system is proposed. Online state monitoring and anlysis，real⁃time updating of simulation model and other technologies are used. UAV online simulation system is designed to auxiliary controll UAV's track correction and speed correction. Intelligence of UAV flight control is improved further. Through UAV mathematical model simulation system and simulation and test system of flight control system hardware in loop，experimental verification is conducted. The effective combination of intelligent correction technology and man in the loop control method is realized. [ABSTRACT FROM AUTHOR]

In this letter, an unusual switching technique is implemented using a fuzzy logic approach. The proposed technique simplifies the conventional method by eliminating the traditional logic-gate design. The fuzzy logic pulse generator acts as a lookup table as well as a pulse generator. On the basis of the modulation index as input, controlled membership functions (MFs) and rules of the fuzzy logic controller open various possibilities of producing pulses directly. The proposed technique is evaluated on the cascaded multi-level inverter with symmetric and asymmetric operations using selective harmonic elimination pulsewidth modulation. MFs are designed on the basis of pre-calculated firing conditions for different modulation index values. Hardware verification is carried out to support the proposed switching technique. [ABSTRACT FROM AUTHOR]